Date: 27./28.06.2011

Participants: Mario Andrighettoni (Microgate), Gilles Orban de Xivry, Lothar Barl (MPE), Martin Kulas (MPIA)

Notes from 2011-06-27

  1. The maximum allowed temperature for the BCU is 50 degree Celsius. The temperature is stored inside the BCU memory.
  2. LBT_EngPanel is a WinXP GUI for writing and reading the BCU registers.
  3. DSP Addresses:
    1. 255: BCU DSP board
    2. 0-1: The DSP-16do board contains two DSP
    3. 2: HVC (actually also address no. 3, but writings to this address are ignored)
    4. 4: HVC (also address no.5 but it is unused)
  4. Firmware supports Jumbo frames: we have to request activation of this feature.
  5. The matlab source code for low level communication is available in /adopt/aoLowLevelComunication
  6. The matlab source code for high level communication: /adopt/aoHighLevelFunction
  7. When writing writing a more than 7 dwords, there is one constaint: the start address must be aligned to 128 bits (4 dword) and the length of the payload must be multiple of 4 dwords.
  8. The following files contain address files:
    1. BCUSlopeCalculator _6_00.map.xml
    2. DSPSlopeCalculator _2_00.map.xml
    3. HVCMainProgram _2_01.map.xml
  9. ARGOS_CodesMemMap_v2.xls contains sane values for Bcu initialization.
  10. Startup procedure:
    1. upload DSP codes.
    2. initialize Bcu.
    3. start BCU.
    4. start CCD.
  11. The file init.m contains example initialization.
  12. dsc_paramSelector: bank selection changes bank on switch Bcu for RTR at DM system. Maybe Argos need its own bit in the dsc_paramSelector for switching memory banks containing the slope offsets (Argos manual 7.3.5).
  13. For installation of LBT_EngPanel: copy all fonts of C:/Windows/fonts to "Eth Driver" folder.

Notes from 2011-06-28

  1. Slopes are in the range from [-1; +1]
  2. Danger: The HVC output is 100 V if the output is enabled.
  3. The CCD pixels are attached at the end of the master record (program has to look at tot_len field of the TDP header.
  4. The Ethernet chip has a queue for incoming frames with a size of eight frames. If there is no space left for an incoming frame, the Ethernet chip crashes.
  5. In this summer, a firmware update is available for the BCU. At the moment, the SDRAM on the DSP16-do boards is running too slow. As a result, the CCD pixels are transfered during the master bcu mechansim, because the DSP boards gets a timeout when copying the pixels from the DSP16-do boards.
  6. The SDRAM/SRAM is byte aligned. The DSP always uses dword aligned addresses.

Pictures

bcu_front.png

bcu_side.png
Topic revision: r2 - 15 Aug 2018, AndrewColson
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