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Understanding LBTO's UMAC

UMAC stands for Universal Motion and Automation Controller. It is a motion controller line manufactured and sold by DeltaTau engineering.

LBTO uses UMAC for two purposes: in OSS subsystem for M2 and M3 position control, and in AGws and AGWs for guiding and wavefront sensing probe positioning, filter wheel control, and focus.

IN UMAC terminology, upload and download are referenced from UMAC side - upload is data transferred from UMAC, download is data transferred to UMAC. We will try to stick with this throughout this text. Host PC references computer connected to UMAC.

UMAC internally uses little-endian architecture (Intel order). For TCP/IP binary arguments, big-endian (network order) is used. Care needs to be taken when passing multibyte numbers (e.g. TCP/IP command parameters, ..).


Name Control Description Firmware
AGW1 oacserver (LUCI) UMAC for AGW off axis - theta, r, focus, filter oacontrol/pmac_fw/AGW1_201.cfg
AGW2 oacserver (LUCI) UMAC for AGW off axis - theta, r, focus, filter oacontrol/pmac_fw/AGW2_200.cfg
AGW3 oacserver (PEPSIPOL) UMAC for AGW off axis - theta, r, focus, filter oacontrol/pmac_fw/AGW3_200_newDPRAM.cfg
AGW4 oacserver (PEPSIPOL) UMAC for AGW off axis - theta, r, focus, filter oacontrol/pmac_fw/AGW4_200_newDPRAM.cfg
AGW5 MODS (MODS) UMAC for AGW off axis - x, y, focus, filter MicroLYNX-7 controller, no firmware
AGW6 MODS (MODS) UMAC for AGW off axis - x, y, focus, filter MicroLYNX-7 controller, no firmware
AGW7 oacserver (PEPSIPOL) UMAC for AGW - focus, filter oacontrol/pmac_fw/AGW7_200.cfg
AGW8 oacserver (PEPSIPOL) UMAC for AGW - focus, filter oacontrol/pmac_fw/AGW8_200.cfg
SX M2 AdSec OSS SX M2 AdSec hexapod etc/absc_IPB_4_counts/SXadsec.cfg HP3
SX M2 rigid OSS SX M2 rigid hexapod etc/absc_IPB_4_counts/Rigid.cfg HP2
DX M2 AdSec OSS DX M2 AdSec hexapod etc/absc_IPB_4_counts/DXadsec.cfg HP1
DX M2 rigid OSS DX M2 rigid hexapod etc/absc_IPB_4_counts/Rigid.cfg HP2
SX M3 OSS SX M3 support (tip,tilt,piston,selector) etc/terc/umac_m3s_config_SX_source.CFG
DX M3 OSS DX M3 support (tip,tilt,piston,selector) etc/terc/umac_m3s_config_DX_source.CFG

UMAC communication board

LBTO's UMACs comes with the communication board, which have RJ-45 (ethernet) and USB port. For old, dual CPU versions, only one control can be active at the time, with USB having priority. For newer, single CPU models, both TCP/IP Ethernet and USB controls can be connected at the same time (at least according to LBTO's rumors; unverified).

The communication board opens single (=only one) connection TCP/IP at the time. The standard configuration for UMAC is to use TCP port 1025. So if you are able to ping the unit, but unable to telnet on port 1025, chances are that some other application is using the connection or that UMAC freezes. Rebooting the UMAC (power off, power on; OWFS/housekeeping board for AGWs, APC PDU for M2 and M3 UMACs) is a good idea to resolve this problem.

UMAC CPU & memory

See Turbo PMAC CPU and Memory.

TCP/IP setup

Follow instructions in PMAC 32-Bit Communication Driver User Manual (from step 4). Please consult IP assigment with mountain/IT before assigning an IP address.

UMAC control concepts

UMAC runs a program written in a custom language. The program is transmitted over TCP/IP in a special packet. Replies are send from UMAC without any packet header. UMAC program is transmited using either VR_PMAC_SENDLINE, VR_PMAC_WRITEBUFFER or (LBTO's preferred; one can argue WRITEBUFFER is better for large transfer) VR_PMAC_GETRESPONSE methods.

You can easily exercices UMAC with pmac (or pmacsend for oacontrol) binaries. Just run the command to get help. One can easily retrieve variables values:

%CODE{"bash"}% [user@host ~]$ pmac -a xx.xx.xx.xx 'I24 I25' $60000\r0\r\x06 [user@host ~]$ pmac -a xx.xx.xx.xx 'I24..34' $60000\r0\r0\r0\r0\r$0\r0\r0\r0\r0\r0\r\x06 %ENDCODE%

and set variables with:

%CODE{"bash"}% [user@host ~]$ pmac -a xx.xx.xx.xx 'I100=1' \x06 [user@host ~]$ pmac -a xx.xx.xx.xx 'I101=0' \x06 %ENDCODE%

UMAC registers

UMAC memory

UMAC program can access memory locations through registers mapings. So e.g. to read "motor estimated rotor magnetization current" value of motor #2, one needs to establish mapping to some M register (7000 below) as follows (send to PMAC from pmac command line or from a file send to PMAC):

%CODE{"asm"}% M7000->Y:$137,24 %ENDCODE%

You can also read memory directly, with R command:

%CODE{"asm"}% RY:$137 %ENDCODE%


Dual-Ported RAM is a memory accessible both to UMAC and host PC. When accessing DPRAM from PC, a single bytes can be addressed. UMAC of cours address DPRAM as 32bit memory - UMAC program can use e.g. DP:$6CFFA,8,16 if it want to access 2 bytes from the middle of 4 byte chunk. The relation between memory offset (passed to DPRAM routines executed from PC) O, DPRAM base address B (found in I24) and DPRAM address A (presented in UMAC programe for DPRAM mapping) is:

A = B + 4 * O

Data are little endian (Intel order), so 0x12 is stored as 0x12 00 00 00.

More on UMAC

Topic revision: r9 - 13 Feb 2020, PetrKubanek
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