Start activities at 09.30
  • Mario Hypothesys: horizontal alignment in board insertion as in the Keck (not well understood!!!) (es: bus not well centered wit crate box). but there is no way of inspection.
  • Roberto Hypothesys: dust in the contacts....
  • System unable to initialize: after various reset and power off we verified communication problems with crate 5, 4-5, 3-4-5, 1-2-3-4-5
  • initialized system and started at 11.15 in the same condition of 20090806
  • @12.45 system stopped disabling coils. Overcurrent protection was the most likely reason
  • Same behavior in the next mirror setting.
  • system restarted at 13.30 still 15.00
  • flashed cold test logics
  • system test started @15.20 and FAILED at 15.4:temporary block FLTimeout and the system start again after a reading.(instead become stuck as the previous logic)
  • started again @16.00 still 16.40
  • Mario is pretty sure that the only difference between the two logics is the bus latency duration (shorter for cold test, the previous as 6.03 unit)
  • We observed that some GC has some "step" lost: the crate 0 was ok, the crates from 1 to 5 lost step
  • Fitted new logic with new cold test timing (line 14 excel spreadsheet)and started the sys @ 17.20
    • first set failed during the test_time_hist2() setting the shell
    • second set again failed in the samecondition
  • Fitted new logic (line 15 excel file attached)
    • unable to set the shell (same fiber timeout)
    • crate 0 board 2, c0 10, c1 b10, c2b8, c5b1 dsp with watchdog expired.

-- MarcoXompero - 2009-08-07
Topic revision: r4 - 07 Aug 2009, MarcoXompero
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