Start activities.

MG change resistors on all DSP boards in order to fix the CORE DSP power supply problem discovered by Mario

6.04 cold test: aveva il nuovo timing e la fifo ridotta (poi nel rifare il fitting si era risolto)

First step:
  • verified logic on board 6.04 with the one provided by Mario
  • test confirmation result of line 9 excel. 6.04 logic. Started on 12.00.
  • No GC error.
  • Timeout FL occurred after 1h and half.(crate 1 board 10)
  • As cold test: OLD timing, reduced FIFO, change time of DSP bus release

Second step:
  • repetition of First step in order to exclude HW problems on the identified board (start: 15:00)
  • after 45 minutes Timeut FL occurred in the same board. Mario verified a slight poor voltage power supply inside. The board was substituted with a spare one and its logic set was upgraded.

Third step:
  • repetition of First step (start 16:40, end 17:55)
  • failure on the SAME board (crate 1 board 10)

Fourth step:

repetition of First Step again (start 18:10, end 19:30)
  • failed on the SAME board (crate 1 board 10)

NOT done:

  • use old Quartus Logic Fitting SW (7.1 version)
  • version 6.05
  • like 6.03 but with DSP communication module resolving all "Known bug" documented in the DSP manual, new ColdTest timing (line 10 EXCEL)

-- MarcoXompero - 2009-08-05
Topic revision: r7 - 07 Aug 2009, MarcoXompero
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